• Introduction
• Programme
• Speaker Profiles
• Slides

Prof. David May

David May is Professor and Head of Computer Science at Bristol University. Before joining the university in 1995, he worked for 16 years in the microelecronics industry, joining Inmos (now STMicroelectronics) at its formation in 1979. He is well known for his work on innovative microprocessors including the Inmos transputer. He is the author of over 100 papers and patents, and has given numerous conference presentations.

In 1990 he was elected a Fellow of the Royal Society for his contributions to computer architecture and parallel computing. David's current research interests are in microprocessor architecture; system design and verification; mobile, wearable and pervasive computing. He maintains active relationships with industry and technology investors, and is on the Technical Advisory Boards of several recent microelectronics design companies. Alongside this, he has advised on intellectual property issues and acted as an expert witness in litigation.

His most recent interests are as CTO of XMOS (microcomputers), director of Mista (location-based services), and co-founder of the Bristol Robotics Labs (fun!).

Kami Sehat

Kami's presentation covers ARC's customisable processor technology and its benefits to embedded system designers. He will elaborate on how ARC manages the development of its range of customisable processors and will discuss ARC's approach to creating customisable System-on-Chip scale intellectual property.

Kami Sehat is the Chief Engineer at ARC. Previously he has worked at ARM, 3Dlabs and Element 14. He holds a doctorate in Computer Design from the University of Cambridge's Computer Laboratory.

Richard Grisenthwaite

Richard will give a technical overview of the Cortex-A8 processor, covering its micro-architecture and implementation methodology. The key architectural features of ARM's highest performance processor will also be described.

Richard Grisenthwaite is the Processor Division lead architect at ARM, being responsible for the ongoing development of the ARM architecture; he has been involved in the development of a number of ARM's cores over the past 8 years.

Sophie Wilson

Sophie will introduce the Firepath processor, explain its Long Instruction Word (LIW) SIMD nature and then illustrate the design of new instructions for it to improve its processing capabilities for Broadband.

Sophie is the Technical Director of DSP Processor Architectures at Broadcom which she joined as part of their acquisition of Element 14, the company which developed Firepath. Previously she worked for Acorn Computers and designed the ARM instruction set.

Alistair Morfey

Alistair will be talking about CCL's new 16- and 32-bit ASIC processors---XAP3, XAP4 and XAP5--- and their associated xIDE development toolkits and SIF debug interfaces. He will be putting this in the context of the kind of chips designed at CCL. These are normally mixed analogue-digital low-power devices for sensor or wireless applications (or both). The ASICs developed at CCL are often part of a complete product development project (e.g developing a complete radio system). This IP is now both used by CCL & sold on the open-market for others to integrate into their own ASICs or FPGAs. The IP is also used by the spinout/spinoff companies from CCL such as CSR and Ember.

Tim Daniels

Tim will discuss the role Structured ASIC's play in today's marketplace. How designers are leveraging the benefits of LSI Logic's Rapidchip to significantly reduce their time to market for custom silicon whilst realising levels of integration/performance not possible in FPGA's.

He will also introduce LSI Logic's reference platform that is enabling customers who are looking for high performance customizable ARM926 processor based structured ASIC's who need to fully debug their system hardware and software before taping out.

Finally, he will also introduce LSI Logic's IP Partner program. This program is aimed at IP providers who want to make their IP available on the LSI Logic's structured ASIC products and give them access to LSI Logic's worldwide customer base.

Tim Daniels, a 12-year veteran of LSI Logic, is manager of technical product marketing and is responsible for European product marketing of ASIC and Platform ASIC. Tim is also part of the worldwide Platform ASIC product marketing team. He has written many papers and articles on various aspects of ASIC design and regularly appears in industry panels. Published Papers in 2005 include the following key conferences: Embedded Systems Conf UK, EuroDesign Conf DE, CMSE05 USA, WEAO/CEPA2 Workshop 05 BE.

Prior to his present role Tim spent three years as a senior design engineer with LSI Logic, responsible for supporting ASIC Design Flows. Previous to this Tim had worked for ES2, Marconi Secure Radio and Plessey Defence Systems where he designed ASIC.s for secure radio systems.

Tim has a Bachelor of Science in electronics from City University, London and is a chartered engineer with the IEE.

Will Robbins

Is there a parallel universe?

The aim of the talk will to be explain how picoChip have made parallel processing work, where other approaches have not been successful. Why picoChip has succeeded at this is that we are reducing the solution space to DSP applications only. So the answer to the title question is no, there is not a parallel universe as far as picoChip are concerned. To solve the problem you must limit the solution space.

Parallel processing always appears to give huge performance, it is just straight multiplication. However practical considerations in reality mean that this huge performance is not obtainable. The picoChip solution takes advantage of the nature of DSP systems, such as their pipeline and stream processing structure, to make optimisations. These optimisations allow the picoArray to remove the headaches of shared memory access and bus contention. Hence picoArray can obtain very high performance from a parallel system. So picoChip are able to implement full WiMAX and HSDPA PHYs on its 300 processor device.

Will Robbins is Design Director at picoChip, where he was a member of the founding team. He has over seventeen years' experience in semiconductor design and design management and in recent years has managed semiconductor design projects that have consistently produced "right first time" silicon for highly complex devices. Will is named as inventor or co-inventor in 29 US patents.

Simon Knowles

It is probably obvious that soft silicon platforms, meaning chips which are made application-specific by software, are increasingly attractive. The massive cost of new chip development can be amortised across multiple market opportunities, and the ballooning complexity of system behaviour can be more safely contained in the world of software. Soft platforms confer the great asset of agility on a systems development, and on a business.

It seems equally obvious that there must be a price to be paid for such agility, in terms of the cost, power, or performance ceiling of a soft platform chip, compared to a dedicated hard implementation. Is this true? Many of the most demanding applications involve "signal" processing -- radio, audio, video, etc. Recent chips demonstrate that it is practical to develop flexible signal processors which are every bit as efficient as fixed-function hardware, even for some applications which demand sustained performance in the tens of GOPs. This talk will discuss the rules of engagement which make such performance and efficiency possible, and the evolution of processor design along this axis.

Co-founder of Icera, a fabless chip start-up developing wireless modem technology based on a new processor called DXP, which implements the concepts of Deep Execution. Icera is headquartered in Bristol and today employs 100 people. Prior to Icera, Simon co-founded and served as VP Silicon for Element 14, a fabless chip start-up developing DSL modems based on a new processor called FirePath. Element 14 was acquired by Broadcom in late 2000, and FirePath technology now dominates the DSL infrastructure market. Prior to Element 14, Simon led the high-end microprocessor design group of STMicro. He was responsible for ST's Chameleon media processor, the first soft platform for MPEG set-top boxes. Simon is an '83 Electrical Science graduate of Cambridge University.